Digital Design Verification Engineer

About the role

Altera, the world’s largest independent FPGA company, is seeking a self‑motivated engineer to join its Design Verification team in Iași. You will work on high‑speed silicon verification for SerDes IP that powers PCIe, Ethernet and other industry‑standard interfaces.

Key responsibilities

• Develop and maintain SystemVerilog/UVM verification environments for SerDes and PHY blocks.
• Write testbenches, functional coverage models and assertions, run simulations and debug RTL and testbench issues.
• Collaborate with design, architecture and analog teams on block‑level and top‑level verification.

Required profile

• BSc in Electrical Engineering, Computer Engineering or equivalent.
• 0–5 years of experience in digital design or verification (including internships or academic projects).
• Strong analytical and debugging mindset with good communication skills in English.

Required skills

• SystemVerilog
• UVM concepts
• Digital design fundamentals: synchronous logic, FSMs, pipelining, clock domain crossing